DRAM is often chosen over other faster types of computer memory because a DRAM cell's smaller size allows many more DRAM cells to be packed into a given chip area. In particular, a typical DRAM cell is comprised of a transistor and a capacitor. Thus, a typical DRAM cell is well suited as a building block for constructing memory on increasingly miniaturized silicon chips.
However, DRAM has drawbacks. With slower speed as compared to other types of memory such as a static random access memory (SRAM), DRAM is limited to less time-critical memory applications. As such, in order to offset DRAM's slower speed, dual port is typically implemented for DRAM in order to reduce access time to a DRAM module. Unfortunately, adapting a dual-port DRAM offsets DRAM's compact size advantage. In particular, a dual-port DRAM necessitates twice as many DRAM cells as that of a single-port DRAM. Thus, using a dual-port DRAM entails significant cost (i.e., on the order of two) and circuits design penalty.
Thus, a need exists for "true" random access and simultaneous write and read memory bandwidth without incurring the cost and penalty of a dual-port conventional DRAM.